1. Field of the Invention
The present invention relates to an image sensor formed of a pixel assembly, each pixel comprising a photodiode.
2. Discussion of the Related Art
FIG. 1 is a diagram of a pixel of an image sensor of “4 transistors” type. The pixel comprises a photodiode 1, an access transistor 2, and a read circuit 3. The anode of the photodiode is grounded. The cathode of photodiode 1 is connected to a row line RL. The drain of access transistor 2 is connected to the source of access transistor 2. The gate of access transistor 2 is connected to a node n. Read circuit 3 is formed of three N-channel MOS transistors T1, T2, T3. The source of transistor T1 and the gate of transistor T2 are connected to node n. The drains of transistors T1 and T2 are connected to a supply voltage Vdd. Transistor T1 is controlled by a reset signal Reset. The source of transistor T2 is connected to the drain of transistor T3 which is controlled by a read signal Read. The source of transistor T3 is connected to a column line Col.
Conventionally, photodiode 1, access transistor 2, and transistors T1, T2, and T3 are formed next to one another in and above a semiconductor substrate, for example, P-type doped. The photodiode comprises P and N doped area formed in the substrate, the P and N areas forming a P/N junction. The transistors are connected to one another as well as to supply voltage Vdd and to column and row lines Col and RL via metallizations formed above the semiconductor substrate in openings of an insulating layer covering the substrate and the transistor gates.
For each pixel, photodiode 1 forms the incident photon capture area. The incident photons cross the insulating layer covering the substrate before they reaching said substrate. On arrival of a photon at the level of photodiode 1, electron-hole pairs are generated. The holes head towards the ground by creating a current through the substrate, and the electrons are “accumulated” in the N-type area of the photodiode which forms a storage “well”.
Conventionally, the pixels of the image sensor are arranged in the shape of a matrix formed of an assembly of rows and columns. The gates of the pixels of the same column are connected to the same column line Col. The access transistors of the pixels of the same row are connected to the same row line RL. The pixels of the image sensor are read row by row in cyclic fashion. Prior to any reading, the reset signal is activated to turn on transistor T1 of each pixel to charge node n to a voltage close to supply voltage Vdd. When a pixel row is read, the read signal is activated to turn on transistors T3 of the pixels of this row. A differential read device then performs for each column a sampling of the voltage present on column line Col, this voltage corresponding to voltage Vn at node n, neglecting an offset. The read pixel row line is then activated to turn on the access transistors of the pixels of this row. For each pixel, the electrons stored in the photodiode head for node n, which results in lowering voltage Vn of node n. The differential read device then performs a second sampling of the voltage present on column line Col. The sampled voltage is all the lower as voltage Vn is low, that is, as the detected light intensity is high. The differential read device then calculates the difference between the first and second sampled voltages, which provides a voltage directly proportional to the number of captured photons per photodiode. Once the reading of a row is over, the selected row line and the read signal are deactivated. The reset signal is then activated again. This sequence of operations is cyclically repeated for each row of the image sensor.
The light intensities measured with this type of “4-transistor” pixel are of good quality. However, when the pixel size is desired to be decreased to increase the number of pixels on a given surface, the sizes of access transistor 2 and of transistors T1 to T3 cannot be sufficiently decreased, to keep a sufficient variation range of the voltage at node n, and the surface area decrease of the pixels is performed to the detriment of the surface taken up by the photodiode. This results in significantly decreasing the sensitivity of the image sensor pixels.
To keep a correct sensitivity while decreasing the pixel size various pixel structures have been devised.
In an image sensor comprising pixels, each comprising an access transistor such as previously described, it is possible to put the read circuits in common. A read circuit is then shared by two pixels. Such a putting in common enables reducing the relative surface area of the transistors with respect to that of the photodiodes. However, such an image sensor requires a slightly more complex addressing circuit. This provides a gain in surface area but this gain remains insufficient for the smallest pixels.
FIG. 2 is an equivalent electric diagram of a pixel of “three-transistor” type which comprises no access transistor. Each pixel comprises a photodiode 30 having its anode connected to ground and its cathode connected to a node n. Node n is connected to a read circuit identical to that of the pixel shown in FIG. 1, the read circuit comprising three transistors T1, T2, and T3.
After each reading of a pixel row, the reset signal connected to transistors T1 of these pixels is activated for a short time to position their node n at a precharge voltage close to that of supply voltage Vdd. The voltage at node n of each pixel then progressively decreases, according to the detected light intensity, until the pixels of this row are read again via transistors T2 and T3.
For a given surface area of a pixel of 3-transistor type, the surface area taken up by the photodiode can be increased with respect to a “4-transistor” pixel shown in FIG. 1. However, the measurements performed by such pixels contain much more noise than those performed by 4-transistor pixels. The measurement noise is proportional to kTC, where k is the Boltzmann constant, T the temperature, and C the equivalent capacitance of the reverse photodiode. Such noise is due to the fact that the precharge of “capacitive” node n is performed through the source/drain resistor of transistor T1. Since a sampling of the precharge voltage of node n cannot be performed prior to the progressive discharge of node n according to the captured photons, the differential reading does not enable suppressing this kTC noise, conversely to the reading of a 4-transistor type pixel.
FIG. 3 is a cross-section view of a “compact” 3-transistor type pixel. The equivalent electric diagram of this pixel is that shown in FIG. 2. Read transistors T1, T2, and T3 are formed in and above a P-type doped substrate 40. In this partial view, only transistor T1 is shown. Transistor T1 comprises a gate 41 insulated from substrate 40 by a thin oxide layer 42 and source/drain areas 43 and 44 placed on each side of gate 41. Substrate 40 and transistors T1, T2, and T3 are covered with an insulating layer 45, itself covered with an amorphous silicon layer 46 in which are formed the photodiodes of the pixels. The upper portion of silicon layer 46 is P-type doped. The rest of the layer is substantially undoped, or intrinsic I, except in lower N-type doped areas. Each pixel comprises a lower N area 47 connected to a source/drain area 43 of transistor T1 of this pixel via a metallization 48 placed in a through opening of insulating layer 45. For each pixel, a filter portion 49 is placed above the amorphous silicon layer. The filter portions let through incident photons exhibiting wavelengths within predefined ranges generally corresponding to those of blue, green, and red.
This pixel structure provides a very large photodiode surface area and thus pixels exhibiting a good sensitivity. However, in addition to the above-mentioned disadvantages relative to 3-transistor pixels, the forming of PIN-type photodiodes in amorphous silicon has many disadvantages, and especially a premature aging of layer 46 in the presence of intense light.